Gary

Gary means gate array: a matrix of logic gates etched to order. In the Amiga 1000 the logic linking the 68000 to the custom chips was spread over dozens of 74-series circuits and PALs. For the A500 and A2000, Commodore gathered it all into one 48-pin chip, and the specification describes it modestly: "miscellaneous control circuitry which provides interface and control for systems using the Amiga custom chip set and a 68000".

The chip has two numbers. The 5718 went into the A2000 and the 5719 into the A500 and A500+, both under part 318072-01. The earliest A2000s, of revision 4, carried a gate array made by Toshiba, with faults: Commodore's service bulletins said to replace it with the MOS version, which became the common one.

In the 32-bit A3000 and A4000 the job passed to Fat Gary, a PLCC that does the same work for a 68030 or 68040. And in the A600 and A1200, Gary was replaced by Gayle, which adds IDE and PCMCIA to it.

Gary's main job is to look at the 68000's seven highest address bits, A17 to A23, and decide who answers. The first 2 MB are Chip RAM; from $200000 to $9FFFFF is the space for Zorro II cards; at $BFxxxx sit the two CIAs; at $C00000 the trapdoor expansion memory, which only exists if the A501 card pulls its EXP pin low; higher up the real-time clock and the custom chip registers; and at the top the Kickstart ROM. The map below shows it.

There is one exception that lives only at start-up: while OVL is high, Gary answers with the ROM at the lowest addresses, so that the 68000 finds its reset vector there. It is CIA-A that drops OVL, and from then on address zero is RAM again.

For each address, Gary produces the right select signals: ROMEN for the ROM, RAMEN for the video memory, RGAE for the custom chip registers, VPA, which tells the 68000 it is talking to a 6800-type peripheral (the CIAs), and the read and write enables for the clock.

The 68000 does not finish a memory cycle on its own: it waits for someone to pull DTACK low, the notice that the data is ready. If DTACK never comes, the processor stops for good. Gary generates it for every device on the board and also for the expansion space, even when nothing is there: so an access to an empty address returns garbage instead of hanging the machine.

Two inputs let the outside world change this. XRDY, pulled by an expansion card, delays DTACK and inserts wait states for slow devices. OVR switches off the internal decoding and DTACK altogether, so a card can take the place of a motherboard device, such as an external ROM, and answer for itself. The specification warns that the trick does not work for replacing Chip RAM or the chip registers: the timing is not reliable.

Gary also steps in when the custom chips are doing DMA. If the processor tries to reach the video bus while Agnus is using it, Gary holds DTACK and the 68000 waits its turn. And when the processor is in the $C00000 area, it asserts the signal that slows the Blitter down.

Beyond addresses, Gary has a string of small jobs that fitted nowhere else. It controls the buffers between the processor bus and the video bus, the CDR, CDW and C4 signals that open the latches at the right moment of the C1 and C3 clocks. It receives the keyboard reset, and it is Gary that pulls the 68000's reset and halt lines.

And it handles a piece of the floppy drive: it latches the motor state when the drive is selected, and buffers the write and motor signals that go to the connector. That is why a drive that will not start its motor can have Gary to blame, and not only CIA-B.

The chip runs off the Agnus clocks: C1 and C3 at 3.58 MHz, 90 degrees apart, and CDAC at 7.14 MHz. It has no clock of its own and no registers: it is pure logic, so it is not programmed, only wired.