National Semiconductor SC/MP

SC/MP is pronounced "scamp" and stands for Simple Cost-effective Micro Processor. National launched it in April 1976 for appliances and controllers, where price per function mattered more than speed. The idea was to build a system with the fewest possible chips around it, and so the SC/MP has its clock oscillator built in, unusual for a PMOS chip.

The first SC/MP (ISP-8A/500) was PMOS, went up to 1 MHz and needed two supplies, +5 V and −7 V. The SC/MP-II, or INS8060 (ISP-8A/600), moved to NMOS, needs only +5 V and takes an oscillator up to 4 MHz. Because a microcycle went from two to four clock periods, in practice it became about twice as fast, not four times.

Signetics appears as an authorised second source and published SC/MP-II documentation, but according to Osborne and Kane it never actually made it.

It has an 8-bit accumulator (AC), an extension register (E), a status register and four 16-bit pointers, P0 to P3. P0 is the program counter. By convention, P1 points to ROM, P2 to RAM and P3 holds the return address for subroutines and interrupts. There are 46 instructions.

There is no stack and no subroutine call instruction. To call a routine, you load its address into a pointer and use XPPC, which swaps that pointer with the program counter; the same instruction takes you back. National's assembler offers a JS that expands into five instructions and seven bytes.

The SC/MP adds 1 to the program counter before fetching each instruction. So, after a reset, it starts at address 0001 and not 0000, and target addresses are always stored as one less.

Addresses are 16 bits, which gives 64 KB, but to save pins there are only 12 address lines: the top 4 bits come out on the data bus, multiplexed. And address arithmetic only touches the bottom 12 bits.

The result is memory in 16 pages of 4 KB. Relative jumps and indexed addressing do not leave the current page, and when the program counter reaches the end of a page it does not move on to the next one: it wraps back to the start of the same page. Changing page means loading the top part of a pointer with dedicated instructions.

There is no dedicated circuit for serial communication: the SIO instruction shifts the E register one bit to the right, putting a bit out on the SOUT pin and reading another from the SIN pin. A whole byte takes eight SIOs in a row.

The bottom three bits of the status register come straight out on three pins, F0 to F2, to light an LED or drive a relay with no extra chips. There are two inputs, Sense A and Sense B, and Sense A also serves as the interrupt request.

The DLY instruction makes the processor wait between 13 and 131,593 microcycles. The MK14 manual uses it with SIO to time serial transmissions. It also has bus request and grant lines (NBREQ, NENIN, NENOUT) for direct memory access and for chaining several SC/MPs to share the same memory.

It was slow for its day: on the original SC/MP, adding an immediate value takes 11 microcycles, 22 µs at 1 MHz, when an 8080 at 2 MHz does it in 3.5 µs. That and the paged memory confined it to controllers, where it also competed with the Fairchild F8. One documented use is the MIPROM lift controller from Montgomery Elevator, with an INS8060N on the board.

The MK14 started from a design by Ian Williamson. When Chris Curry, of Science of Cambridge, asked National for prices, the company offered a complete design for free, built with its IntroKit and its keyboard kit, in exchange for a contract to buy the parts. The kit came out at 39.95 pounds and the first ones started reaching customers in February 1978.

The MK14's crystal is 4.43 MHz, the PAL colour subcarrier frequency, made by the million for televisions. That is about 10% above the 4 MHz maximum that the INS8060 datasheet gives.