Z80N (Spectrum Next)

The Next began in 2010 in Brazil, as a variant of the TK95, a Spectrum clone. In 2016, Victor Trucco and Fabio Belavenuto presented the TBBlue, a board for enthusiasts; with Henrique Olifiers, the project moved to the United Kingdom and brought in Rick Dickinson, the designer of the original cases.

The initial idea was to use a real Z80, but the design moved to a Xilinx Spartan-6 FPGA, so that hardware sprites, scrolling and other new features could fit inside the machine itself. An FPGA is a chip full of logic blocks that wire themselves together according to a file loaded at start-up: you describe the circuit, and the chip becomes that circuit. It is not software emulation.

The machines from the first Kickstarter use the Spartan-6 XC6SLX16; those from the second, an Artix-7 XC7A15T; those from the third, a larger Artix-7 XC7A35T. The Z80N is the same in all of them.

The Z80N starts from the T80, a Z80-compatible core written in VHDL by Daniel Wallner between 2001 and 2002 and published on OpenCores, used in many recreations of computers and arcade machines.

The header of the t80n.vhd file, in the Next's code, says who did what: Fabio Belavenuto fixed part of a bug in the wait states, Victor Trucco, Fabio Belavenuto and Garry Lancaster added the new instructions, and Charlie Ingley fixed the wait logic completely. Garry Lancaster is also the author of NextZXOS and NextBASIC.

The FPGA hardware description is published on GitLab, under the GPL3 licence. The rest of the project (schematics, board, case) is not open.

The Z80N instructions use the ED prefix, on opcodes that Zilog's Z80 did not document. Some do what Spectrum programmers spent years writing by hand: MUL D,E multiplies two 8-bit numbers and leaves the 16-bit result in DE (the original Z80 has no multiplication), SWAPNIB swaps the two 4-bit halves of the accumulator, MIRROR A reverses the order of the bits, ADD HL,A adds the accumulator to a register pair, and PUSH nn pushes a fixed value onto the stack.

Others are for graphics. LDIX and LDIRX copy memory like LDI and LDIR, but skip the bytes equal to the accumulator: that is sprite transparency in a single instruction. LDPIRX fills an area with an 8-byte pattern, and LDWS copies vertically to the Layer 2 screen. PIXELAD works out the address of a pixel on the Spectrum screen from its coordinates, and PIXELDN moves down one line; anyone who has done that sum on the Spectrum's interleaved screen knows how much code this saves.

There are also NEXTREG, which writes directly to the Next's configuration registers without going through the ports, OUTINB, TEST, JP (C), and the multi-bit rotates and shifts (BSLA, BSRA, BSRL, BSRF, BRLC), which only exist from version 2 of the core onwards.

The speed is chosen in the Next's register 0x07: 3.5, 7, 14 or 28 MHz. 28 MHz only works from version 3.0 of the core. After a reset the processor goes back to 3.5 MHz, the speed of the original Spectrum, and it is at that speed that old software, with its timing tricks, behaves as it should.

28 MHz is not exactly eight times faster: according to the Next documentation, from core 3.0.5 onwards every instruction fetch and memory read takes an extra wait state, and a NOP goes from 4 to 5 cycles. And when the expansion bus is active, the speed is capped at 3.5 MHz, so that old peripherals keep working.

The Next's memory (1 or 2 MB on the first machines) is far larger than the 64 KB the Z80N sees at any one time; it comes into the processor's window in 8 KB blocks.